Wang, C., et al.: Congestion-aware network-on-chip router architecture. Wang, C., et al.: Design and evaluation of a high throughput qos-aware and congestion-aware router architecture for network-on-chip. Kim, J., et al.: Flattened butterfly topology for on-chip networks. ACM, New York (2006)ĭas, R., et al.: Design and evaluation of a hierarchical on-chip interconnect for next-generation cmps. 2(4), 398–412 (1991)īalfour, J., et al.: Design tradeoffs for tiled cmp on-chip networks. 88–598 (2008)Īgarwal, A.: Limits on interconnection network performance. In: IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, pp. Kluwer Academic Publishers, Norwell (2003)īell, S., et al.: Tile64 - processor: a 64-core soc with mesh interconnect. Evaluation results shown that, the proposed PDNOC provides up to 25 % improvement in execution time over concentrated mesh, and 3.6x better energy delay product over fully connected diagonal network. We implement a full system simulation environment using SPLASH-2 benchmarks. The key insight that enables the PDNOC is that most communication patterns in real-world applications are hot-spot and bursty. We analyse the partially diagonal network in terms of area usage, power consumption, routing algorithm and implementation complexity. Therefore in this paper, we propose a novel Partially Diagonal Network-on-Chip (PDNOC) design that takes advantage of both heterogeneous network topology and congestion-aware application mapping. The efficiency can also be optimized by proper mapping of applications. Performance and power consumption of an on-chip interconnect are directly affected by the network topology. With the constantly increasing of number of cores in multicore processors, more emphasis should be paid to the on-chip interconnect.
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